The present invention generally relates to semiconductor design technologies, and, more particularly, to a semiconductor memory device having a precharge signal generator capable of securing a timing margin in case of driving at a high frequency, without increase in its size and current consumption.
Generally, a write operation of a DRAM is performed by a write command and a write-precharge-command. Upon input of the write command, only the write operation is carried out, in which data is stored in a unit memory cell designated by a corresponding address. Meanwhile, upon input of the write-precharge-command, the write operation followed by an operation of precharging an activated word line is conducted. In addition, the write command and the write-precharge-command are distinguished from each other by a logic level of a specific address.
The following is a detailed description of a precharge signal generator for generating a precharge command to precharge a corresponding bank that becomes active by the write operation.
FIG. 1 is a block diagram showing a structure of a conventional precharge signal generator being used in a semiconductor memory device.
Referring to FIG. 1, the conventional precharge signal generator includes a clock buffer 10 for receiving an internal clock CLK and generating a pulse clock CLKP, a write interval signal generator 20 for producing a write interval signal T_APCG in response to a column address AY<8> and an internal write signal CASP6WT<0>, and a signal generator 30 for generating a precharge signal APCG<0> after a delay time corresponding to a write-recovery time in response to the write interval signal T_APCG.
For reference, the write interval signal generator 20 and the signal generator 30 are blocks which generate the precharge signal APCG<0> to precharge a word line activated within a first bank. As such, to generate a precharge signal APCG<0:3> for each bank in the device, the internal write signal CASP6WT, activated with bank information and write information, is applied to the write interval signal generator 20. That is, the conventional precharge signal generator is provided with plural write interval signal generators and signal generators for precharging each bank within the semiconductor memory device, and precharges a specific bank in response to an activation of a corresponding signal out of a plurality of internal write signals CASP6WT<0:3>, which is activated depending on the bank information.
Further, the write-recovery time used herein is the time that elapses after the inflow of data stored in a cell into a bit line sense amplifier (which amplifies the input data) (not shown) until an update of the cell with data from outside in the bit line sense amplifier by an activation of a corresponding word line. This write-recovery time is decided by setting a write-recovery-information signal TWR<3:5> upon an initial operation. For example, if the write-recovery time is 3, the write-recovery-information signal TWR<3> is activated to a logic high level and the other signals TWR<4>and TWR<5> are inactivated to a logic low level.
In succession, if the column address AY<8> has a logic high level, this implies that the write-precharge-command is applied, and if the column address AY<8> has a logic low level, this implies that the write command is applied.
Meanwhile, the signal generator 30 is embodied by a multiplicity of shifters which delay the write interval signal T_APCG for a delay time corresponding to the write-recovery-information signal TWR<3:5>.
FIG. 2 is a waveform diagram describing the operation of the conventional precharge signal generator shown in FIG. 1.
First, a write-precharge-command WTWAP<0> is applied and its corresponding data is then received from outside. When the reception of the data is completed, the internal write signal CASP6WT<0> is activated in synchronization with the pulse clock CLKP.
Then, the write interval signal generator 20 activates the write interval signal T_APCG in response to the internal write signal CASP6WT<0> and the column address AY<8>.
Next, the signal generator 30 activates the precharge signal APCG<0> in synchronization with a rising edge of the pulse clock CLKP after a delay time corresponding to the write-recovery-information signal TWR<3:5>, starting from the activation time of the write interval signal T_APCG. At this time, the time corresponding to the write-recovery-information signal TWR<3:5> is counted by the pulse clock CLKP outputted from the clock buffer 10. For reference, it is assumed that the write-recovery time is set to 3 clocks and thus the write-recovery-information signal TWR<3> is activated.
On the other hand, as for a case where a write-precharge-command WTWAP<1> is applied for making a second bank active, the operation is performed in the same way, and therefore, details thereof are omitted here for simplicity.
As mentioned above, upon application of the write-command with precharge information, the conventional precharge signal generator in the semiconductor memory device counts a delay time corresponding to an internal latency and a write-recovery on the basis of the pulse clock with the same frequency as the internal clock, and thereafter generates the precharge signal. Thus, the more the delay time increases, the more it needs shifter devices for counting.
As a result, the conventional precharge signal generator has several problems in that a timing margin of the generator is reduced in case of driving at a high internal clock frequency, and its size and current consumption increase due to the increase of shifters in the signal generator.